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| 8-BIT SCANNABLE REGISTER SY10E241 SY100E241 FEATURES s 1000ps max. CLK to output s Extended 100E VEE range of -4.2V to -5.5V s s s s SHIFT overrides HOLD, /LOAD control Asynchronous Master Reset Pin-compatible with E141 Fully compatible with industry standard 10KH, 100K ECL levels s Internal 75K input pulldown resistors s Fully compatible with Motorola MC10E/100E241 s Available in 28-pin PLCC package DESCRIPTION The SY10/100E241 are 8-bit shiftable registers designed for use in new, high-performance ECL systems. Unlike the E141, the E241 features internal data feedback organized such that the SHIFT control overrides the HOLD, /LOAD control. Thus, the normal operations of HOLD and LOAD can be toggled with a single control line without the need for external gating. This configuration also enables switching to scan mode with the single SHIFT control line. The eight inputs D0-D7 accept parallel input data, while S-IN accepts serial input data when in shift mode. Data is accepted a set-up time before the rising edge of CLK. Shifting is also accomplished on the rising clock edge. A HIGH on the Master Reset pin (MR) asychronously resets all the registers to zero. BLOCK DIAGRAM S-IN D D0 Q R Q0 PIN CONFIGURATION D5 VCCO SEL0 NC D7 D6 Q7 25 24 23 22 21 20 19 SEL1 CLK MR VEE S-IN D0 D1 26 27 28 1 2 3 4 5 6 7 8 9 10 11 18 17 Q6 Q5 VCC NC VCCO Q4 Q3 D D1 - D6 Q R Q1 - Q6 TOP VIEW PLCC J28-1 16 15 14 13 12 BITS 1-6 D2 D3 D D7 SEL1 (HOLD/LOAD) SEL0 (SHIFT) CLK MR Q R Q7 PIN NAMES Pin D0-D7 S-IN SEL0 SEL1 CLK MR Q0-Q7 VCCO Function Parallel Data Inputs Serial Data Input SHIFT Control HOLD, /LOAD Control Clock Master Reset Data Outputs VCC to Output D4 VCCO Q0 Q1 Q2 Rev.: C Amendment: /1 1 Issue Date: February, 1998 Micrel SY10E241 SY100E241 TRUTH TABLE SEL0 L L H SEL1 L H X Function Load Hold Shift (Dn to Dn+1) DC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0C Symbol IIH IEE Parameter Input HIGH Current Power Supply Current 10E 100E -- -- 125 125 150 150 -- -- 125 125 150 150 -- -- 125 144 150 173 TA = +25C TA = +85C Typ. -- Max. 150 Unit A mA Condition -- -- Min. Typ. Max. Min. Typ. -- -- 150 -- -- Max. Min. 150 -- AC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0C Symbol fSHIFT tPLH tPHL tS Parameter Max. Shift Frequency Propagation Delay to Output CLK MR Set-up Time D SEL0 (SHIFT)350 SEL1 (HOLD/LOAD) S-IN Hold Time D SEL0 (SHIFT) SEL1 (HOLD/LOAD) S-IN Reset Recovery Time Minimum Pulse Width CLK, MR Within-Device Skew Rise/Fall Time 20% to 80% 700 625 600 175 200 400 125 200 100 50 300 900 400 -- 300 900 750 725 25 -- 250 -100 -25 -200 -250 100 600 -- 60 525 -- 975 975 -- 350 -- -- -- -- -- -- -- -- -- 800 TA = +25C 700 625 600 175 200 400 125 200 100 50 300 900 400 -- 300 900 750 725 25 -- 250 -100 -25 -200 -250 100 600 -- 60 525 -- 975 975 -- 350 -- -- -- -- -- -- -- -- -- 800 TA = +85C Max. -- 975 975 ps 175 200 400 125 200 100 50 300 900 400 -- 300 25 -- 250 -100 -25 -200 -250 100 600 -- 60 525 -- -- -- ps -- -- -- -- -- -- -- 800 ps ps ps ps -- -- 1 -- -- -- Unit MHz ps 625 600 750 725 Condition -- -- 700 900 Min. Typ. Max. Min. Typ. Max. Min. Typ. tH tRR tPW tskew tr tf NOTE: 1. Within-device skew is defined as identical transitions on similar paths through a device. PRODUCT ORDERING CODE Ordering Code SY10E241JC SY10E241JCTR SY100E241JC SY100E241JCTR 2 Package Type J28-1 J28-1 J28-1 J28-1 Operating Range Commercial Commercial Commercial Commercial Micrel SY10E241 SY100E241 28 LEAD PLCC (J28-1) Rev. 03 3 Micrel SY10E241 SY100E241 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA FAX + 1 (408) 980-9191 + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated 4 |
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